1. Field of the Invention
The present invention relates to a semiconductor memory, and particularly to a highly integrated semiconductor memory with a decreased area.
2. Description of the Related Art
High integration and decrease in area are required of a semiconductor memory. The high integration and decrease in area of a semiconductor memory depends upon the advancement of micro-lithography. With the micro-lithography, a micro-lithography process based on miniaturization of a processing dimension, such as a 0.2 .mu.m process and a 0.15 .mu.m process, has been developed. However, there will be a limit to such miniaturization of a processing dimension.
In order to realize high integration and decrease in area of a semiconductor memory, the arrangement of memory cells and sense amplifiers on a circuit, as well as the micro-lithography are important. This is because the area of the semiconductor memory is mostly occupied with the memory cells and the sense amplifiers.
As described in Japanese Laid-open Publication No. 2-4467, as a method for arranging memory cells and sense amplifiers, a folded bit line method and an open bit line method are known. According to the folded bit line method, a bit line and a / bit line are arranged on one side of a sense amplifier portion (hereinafter, the symbol "/" refers to a logical NOT bar). According to the open bit line method, a bit line is arranged on one side of a sense amplifier portion, and a / bit line is arranged on the other side of the sense amplifier portion. The folded bit line method has the advantage of resistance to noise. However, in this method, memory cells are arranged at every other crossing point of bit lines and word lines, so that high integration cannot be achieved. The open bit line method has the disadvantage of vulnerability to noise. However, memory cells can be arranged densely, so that high integration can be realized.
In recent years, since the high integration of a semiconductor memory has advanced, and noise or the like caused by a coupling capacitance between lines becomes significant, the folded bit line method does not necessarily have the advantage of the resistance to noise. Because of this, an open bit line method capable of realizing high integration is being considered.
As a sense amplifier of a semiconductor memory, as described in Japanese Laid-open Publication No. 2-4467, a sense amplifier composed of a CMOS circuit using PMOS transistors and NMOS transistors is known.
However, when both a PMOS transistor and an NMOS transistor are used for a sense amplifier, a well is required for separating the PMOS transistor and the NMOS transistor. This makes it difficult to decrease the area of the sense amplifier.
If the open bit line method is used, a pair of bit lines will become imbalanced, which worsens the sensitivity of a sense amplifier, resulting in a delay of access time and an increased cycle time.